Advertisement
Verilog-Perl
Verilog-Perl offers an overview of Verilog language packages for Perl....
Verilog::SigParser
Verilog::SigParser is a Perl module for signal parsing for Verilog language files....
Verilog::Parser
Easily parse Verilog language files...
Verilog::CodeGen
Verilog::CodeGen module is a Verilog code generator....
Verilog::Pli::Net
Verilog::Pli::Net is a Verilog PLI tied net access hash....
Text::EP3::Verilog
Text::EP3::Verilog Perl module contains a verilog extension for the EP3 preprocessor....
Python module extension Verilog verilog extension EP3 preprocessor
Hardware::Verilog::Parser
A complete grammar for parsing Verilog code using Perl...
Verilog::Netlist::Net
Verilog::Netlist::Net is a Net for a Verilog Module....
Parse::BBCode
Module to turn BBCode into HTML or plain text...
Parse::Marpa
Generate Parsers from any BNF grammar...
Kismet Parse
Kismet Parse project can be used after kismet has sniffed 802.11 traffic and produced .network files....
Mac sniffer map MAC address wireless access point 802.11 sniffer
Parse::PlainConfig
Parser for plain-text configuration files...
Parse::Indented
Given a Pythonesque set of indented lines, parses them into a convenient hierarchical structure...
Perl module parser lines hierarchical structure indented lines
Parse::Template
Parse::Template was initially created to serve as a code generator for the Parse::Lex class....