Verilog::SigParser

Verilog::SigParser is a Perl module for signal parsing for Verilog language files.
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Verilog::SigParser Ranking & Summary

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  • Rating:
  • License:
  • Perl Artistic License
  • Price:
  • FREE
  • Publisher Name:
  • Wilson Snyder
  • Publisher web site:
  • http://search.cpan.org/~wsnyder/Verilog-Perl-3.035/Parser/Parser.pm

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Verilog::SigParser Description

Verilog::SigParser is a Perl module for signal parsing for Verilog language files. Verilog::SigParser is a Perl module for signal parsing for Verilog language files.SYNOPSIS use Verilog::Preproc; use Verilog::SigParser; my $pp = Verilog::Preproc->new(keep_comments=>0,); my $parser = new Verilog::SigParser; $parser->parse_preproc_file ($pp); # The below described callbacks are then invokedVerilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined.See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application. For a higher level interface to this package, see Verilog::Netlist. Requirements: · Perl


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