Verilog::Netlist Verilog Netlist
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Perl module perl Verilog Verilog Netlist Netlist

Verilog::Netlist Description

Verilog Netlist Verilog::Netlist is a Perl module with the Verilog Netlist.SYNOPSIS use Verilog::Netlist; # Setup options so files can be found use Verilog::Getopt; my $opt = new Verilog::Getopt; $opt->parameter( "+incdir+verilog", "-y","verilog", ); # Prepare netlist my $nl = new Verilog::Netlist (options => $opt,); foreach my $file ('testnetlist.v') { $nl->read_file (filename=>$file); } # Read in any sub-modules $nl->link(); $nl->lint(); $nl->exit_if_error(); foreach my $mod ($nl->top_modules_sorted) { show_hier ($mod, " ", "", ""); } sub show_hier { my $mod = shift; my $indent = shift; my $hier = shift; my $cellname = shift; if (!$cellname) {$hier = $mod->name;} #top modules get the design name else {$hier .= ".$cellname";} #append the cellname printf ("%-45s %s ", $indent."Module ".$mod->name,$hier); foreach my $sig ($mod->ports_sorted) { printf ($indent." %sput %s ", $sig->direction, $sig->name); } foreach my $cell ($mod->cells_sorted) { printf ($indent. " Cell %s ", $cell->name); foreach my $pin ($cell->pins_sorted) { printf ($indent." .%s(%s) ", $pin->name, $pin->netname); } show_hier ($cell->submod, $indent." ", $hier, $cell->name) if $cell->submod; } }Verilog::Netlist reads and holds interconnect information about a whole design database.See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application.A Verilog::Netlist is composed of files, which contain the text read from each file.A file may contain modules, which are individual blocks that can be instantiated (designs, in Synopsys terminology.)Modules have ports, which are the interconnection between nets in that module and the outside world. Modules also have nets, (aka signals), which interconnect the logic inside that module.Modules can also instantiate other modules. The instantiation of a module is a Cell. Cells have pins that interconnect the referenced module's pin to a net in the module doing the instantiation.Each of these types, files, modules, ports, nets, cells and pins have a class. For example Verilog::Netlist::Cell has the list of Verilog::Netlist::Pin (s) that interconnect that cell. Requirements: · Perl

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