Verilog Flattener Flatten verilog module / design, flatten instances / hierarchies
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Hierarchy Verilog RTL

Verilog Flattener Description

Verilog Flattener was designed as a Java-based and accessible utility that takes all the verilog RTL files along with the top verilog module name and traverses the entire hierarchy starting from the top. It removes each of the instances by pulling that's functionality in the top module. Please note that it supports mainly the synthesizable verilog constructs.

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