Jove Open Verilog hardware verification environment for the Java Platform
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simulate verify verifier verilog simulator verify hardware Verilog verification

Jove Description

Open Verilog hardware verification environment for the Java Platform Jove is a free set of Java tools and APIs to enable Verilog hardware design verification using the Java programming language. Jove contains components that accomplish the following:· Verilog simulator interaction (via PLI 2.0, aka VPI)· standalone behavioral simulation (i.e. a discrete event simulator)· thread and event synchronization· design verification abstractions (e.g. clock-relative signal access, mailboxes, semaphores)· constraint-based randomization· Verilog shell generationIn other words, Jove provides facilities similar to Synopsys Vera, Cadence Testbuilder, and (formerly) Verisity Specman.NOTE: Jove is released and licensed under the terms of the Open Software License. Here are some key features of "Jove": · Jove leverages the Java language, a standard, well-defined, high-productivity object-oriented programming language. Alternative tools introduce proprietary languages, or use more complex, less productive languages, like C/C++ or Perl. · Jove leverages Java libraries, including the extensive Java runtime library, the JUnit test framework, and thousands of third-party libraries. Java libraries tend to be much easier to integrate than libraries in earlier mature languages, such as C/C++. · Jove leverages Java tools, such as Javadoc and Eclipse. The Eclipse IDE, for instance, provides Jove users with a free, powerful GUI debugger. · Jove leverages Java Virtual Machine technology, arguably the most mature, high-performance VM technology available, with performance rivaling compiled languages in most cases. · Jove leverages the experience of a software-oriented team executing the complete lifecycle of a very complex ASIC verification project. It addresses the limitations encountered using other tools during that project. Requirements: · Java

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