Covered Covered is a Verilog code coverage analysis tool.
Download

Covered Ranking & Summary

Covered Tags

code code analysis code coverage Verilog Verilog analysis Covered

Covered Description

Covered is a Verilog code coverage analysis tool. Covered is a Verilog code coverage analysis tool. Covered can be useful for determining how well a diagnostic test suite is covering the design under test.Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document.When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?".When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. What's New in This Release: · Fixed compilation warnings when compiling on 64-bit Mac OS X and Debian-based platforms. · Updates to build scripts to help downstream Debian releases builds. · Fixed bug 2880705. $Id: keywords containing newlines are now handled properly. Additionally, fixing issues with multiply instantiated modules within a generate block. · Fixed bug 2881869. Fixed a stack overflow issue in the gen_item_resolve function that would cause segmentation faults when too many items were being generated within a single generate block. · Fixed bug 2882433. Fixed the "ERROR! Parameter used in expression but not defined in current module" error when a generated module instance has a parameter override of a parameter with the same name as the parameter within the module that contains the generate block.

Covered Related Software