sp_preprocsp_preproc is a SystemPerl Preprocessor. | |
Download |
sp_preproc Ranking & Summary
Advertisement
- License:
- Perl Artistic License
- Price:
- FREE
- Publisher Name:
- Wilson Snyder
- Publisher web site:
- http://search.cpan.org/~wsnyder/Verilog-Perl-3.035/Parser/Parser.pm
sp_preproc Tags
sp_preproc Description
sp_preproc is a SystemPerl Preprocessor. sp_preproc is a SystemPerl Preprocessor.SYNOPSIS sp_preproc sp_preproc takes a .sp (systemperl) file and creates the SystemC header and C files.It is generally only executed from the standard build scripts.ARGUMENTS--helpDisplays this message and program version and exits.--hier-onlyRead only hierarchy information, ignore all signal information. Useful for faster generation of sp_lib files.--inlineEdit the existing source code "inline". Similar to the Verilog-mode AUTOs. Use --inline --noautos to remove the expanded automatics.--libfileFilename to write a list of sp_cells into, for later use as a --libcell to another sp_preproc run.--libcellFiles listed before --libcell will be preprocessed or inlined as appropriate. Files after noexpand will only be used for resolving references, they will not be linked, linted, or otherwise checked. --nolibcell can be used to re-enable checking of subsequent files.--ncscCreate output files compatible with Cadence NC-SystemC.--nolintDisable lint style error checks, such as required to run doxygen on the SystemPerl output.--preprocPreprocess the code, writing to separate header and cpp files.--trace-duplicatesInclude code to trace submodule signals connected directly to a parent signal, generally for debugging interconnect. Without this switch such signals will be presumed to have the value of their parent module's signal, speeding and compressing traces.--tree filenameWrite a report showing the design hierarchy tree to the specified filename. This format may change, it should not be parsed by tools.--noautosWith --inline, remove any expanded automatics.--verboseShows which files are being written, or are the same.--write-verilog filenameWrite the SystemC interconnections in Verilog format to the specified filename. Note this does not include logic, it only contains module ports and cells.-MMakes the dependency listing (similar to cpp -M).-Dvar=valueSets a define to the given value (similar to cpp -D).-f fileParse parameters from the given file. Requirements: · Perl
sp_preproc Related Software